1. Field of the Invention
The present invention relates to a semiconductor memory wherein a bit line is precharged to a predetermined potential for reading data.
2. Description of the Prior Art
In the semiconductor memory, the timing of activating a sense amplifier is sometimes varied due to the effects of variations in production which occur during formation of memory cell arrays over a silicon substrate, or variations in environmental factors, such as temperature condition, voltage condition, etc., and this variation in timing results in an unstable reading operation. An example of a semiconductor memory designed such that such effects are corrected to realize a stable reading operation is shown in FIG. 11. In the semiconductor memory 500 of FIG. 11, the timing of occurrence of a potential difference between bit lines is determined using actual memory cells (replica memory cells), and the sense amplifier is activated according to the determined timing (see Japanese Laid-Open Patent Publication No. 2001-351385 (page 6; FIG. 1)).
The semiconductor memory 500 includes a memory cell array 510, a predecoder 520, a word line driver 530, sense amplifiers 540, a replica column 550, an address logic circuit 560, and a column I/O logic circuit 570.
The memory cell array 510 includes a plurality of memory cells 511 arranged in a matrix configuration. A column of memory cells 511 are connected through a pair of bit lines to a corresponding one of the sense amplifiers 540.
The predecoder 520 decodes part of an address signal and outputs the result of the decoding to the word line driver 530.
The word line driver 530 activates a word line selected according to the address decode result of the predecoder 520.
The sense amplifiers 540 detects a voltage difference between the pair of bit lines according to an enable signal output from the column I/O logic circuit 570.
The replica column 550 includes a plurality of replica memory cells 551 aligned in a column direction and placed along a side of the memory cell array 510.
Each of the replica memory cells 551 is a replica of the memory cell 511 and has a pass transistor 551a. The gate terminal of the pass transistor 551a is connected to the address logic circuit 560 through a dummy word line. A predetermined number of replica memory cells 551 are connected to a pair of dummy bit lines which are connected to the column I/O logic circuit 570.
The column I/O logic circuit 570 detects a potential difference between the pair of dummy bit lines and outputs the result of the detection as an enable signal to the sense amplifiers 540.
In the above-described structure, when reading information stored in the memory cells 511, an input address is decoded by the address logic circuit 560 and the word line driver 530 to select a specific memory cell 511. The selected memory cell 511 produces a potential difference between the pair of bit lines.
Meanwhile, the address logic circuit 560 activates the gate terminals of the pass transistors 551a of a predetermined number of replica memory cells 551. As a result, an enable signal is output from the column I/O logic circuit 570. Since the replica memory cell 551 is a replica of the memory cell 511, the timing of occurrence of the potential difference between the dummy bit lines, i.e., the timing of outputting the enable signal, is substantially the same as the timing of occurrence of the potential difference between the bit lines of the memory cell 511. Receiving the enable signal, the sense amplifiers 540 detect the potential difference occurring between the pair of bit lines.
In the semiconductor memory 500, the timing of occurrence of a potential difference between the bit lines is determined using the replica column 550 as described above. Therefore, the effects of variations in production, temperature condition, voltage condition, etc., can be corrected.
When power reduction is required in a semiconductor integrated circuit, it can be achieved by decreasing the supply voltage. However, in general, the threshold voltage cannot be decreased so much in view of suppression of drain leakage of transistors. Therefore, when the semiconductor integrated circuit operates at a low voltage in a process of relatively-high threshold voltage, a variation in transistor performance becomes considerably large. Especially in memory cells of a semiconductor memory in which very small transistors are used, the variation is still larger.
Thus, when the timing generation function which uses the replica column 550 as in the semiconductor memory 500 operates at a low voltage near a threshold voltage, the transistor capacity of a memory cell can be far smaller than that of a corresponding replica memory cell, causing an error in the operation.
A possible way to avoid errors during a low voltage operation is to delay a timing using, for example, a delay circuit. However, this results in a redundant circuit structure and increases the circuit area.